32-PIN
Abstract: DS1249W DS1249W-100 DS1249W-150
Text: DS1249W 3.3V 2048kb Nonvolatile SRAM www.maxim-ic.com FEATURES § § § § § § § § PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation
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PDF
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DS1249W
2048kb
100ns
32-pin
DS1249W
150ns
32-PIN,
DS1249W-100
DS1249W-150
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E99151
Abstract: DS1249W DS1249W-100 DS1249W-100IND MDT32
Text: 19-5633; Rev 11/10 DS1249W 3.3V 2048kb Nonvolatile SRAM www.maxim-ic.com FEATURES • • PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles
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Original
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PDF
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DS1249W
2048kb
100ns
32-pin
MDT32
E99151
DS1249W
DS1249W-100
DS1249W-100IND
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MH89793
Abstract: MT8979 MT9079
Text: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,
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Original
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PDF
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MH89793
DS5419
2048kbit/s
MT8979,
MT9079
MH89793
MT8979
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32-PIN
Abstract: DS1249W DS1249W-100 DS1249W-100IND DS1249W-150 DS9034PC DS9034PCI
Text: DS1249W 3.3V 2048kb Nonvolatile SRAM www.maxim-ic.com FEATURES § § § § § § § § PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation
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Original
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PDF
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DS1249W
2048kb
100ns
32-pin
DS9034PC
DS9034PCI
DS1249W
DS1249W-100
DS1249W-100IND
DS1249W-150
DS9034PCI
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Untitled
Abstract: No abstract text available
Text: DS1249W 3.3V 2048kb Nonvolatile SRAM www.maxim-ic.com FEATURES § § § § § § § § PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation
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Original
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PDF
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DS1249W
2048kb
100ns
32-pin
DS1249W
150ns
32-PIN,
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MH89793
Abstract: MT8979 MT9079
Text: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,
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Original
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PDF
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MH89793
DS5419
2048kbit/s
MT8979,
MT9079
MH89793
MT8979
|
MH89793
Abstract: MT8979 MT9079 zarlink PDIP
Text: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,
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Original
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PDF
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MH89793
DS5419
2048kbit/s
MT8979,
MT9079
MH89793
MT8979
zarlink PDIP
|
Untitled
Abstract: No abstract text available
Text: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,
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Original
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PDF
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MH89793
2048kbit/s
MT8979,
MT9079
DS5419
MH89793
|
Untitled
Abstract: No abstract text available
Text: MH89792 E1 Line Interface Unit LIU Data Sheet Features DS5712 Issue 4 March 2002 Ordering Information • Complete primary rate 2048kbit/s E1line driver and receiver with clock recovery • Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transmit and
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Original
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PDF
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MH89792
2048kbit/s
MT8979,
MT9079
490mm2
DS5712
MH89792-1
MH89792-2
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MH89792
Abstract: MH89792-1 MH89792-2 MT8979 MT9041 MT9079 PCM30 RJ48C
Text: MH89792 E1 Line Interface Unit LIU Data Sheet Features DS5712 Issue 4 March 2002 Ordering Information • Complete primary rate 2048kbit/s E1line driver and receiver with clock recovery • Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transmit and
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Original
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PDF
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MH89792
DS5712
2048kbit/s
MT8979,
MT9079
490mm2
MH89792-1
MH89792-2
MH89792
MH89792-1
MT8979
MT9041
PCM30
RJ48C
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MH89793
Abstract: MT8979 MT9079 EW 90
Text: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,
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Original
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PDF
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MH89793
DS5419
2048kbit/s
MT8979,
MT9079
MH89793
MT8979
EW 90
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MH89792
Abstract: MT9079 PCM30 RJ48C MH89792-1 MH89792-2 MT8979 MT9041 TPEC
Text: MH89792 E1 Line Interface Unit LIU Preliminary Information ISSUE 4 Features • • • • • • • • • Complete primary rate 2048kbit/s E1line driver and receiver with clock recovery Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transmit and
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Original
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PDF
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MH89792
2048kbit/s
MT8979,
MT9079
490mm
MH89792
PCM30
RJ48C
MH89792-1
MH89792-2
MT8979
MT9041
TPEC
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MH89793
Abstract: MT8979 MT9041 MT9079 PCM30 RJ48C RZA 18 RJ48
Text: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,
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Original
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PDF
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MH89793
2048kbit/s
MT8979,
MT9079
MH89793
MT8979
MT9041
PCM30
RJ48C
RZA 18
RJ48
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square root extractor
Abstract: RXB 24 MH89792 MH89792-1 MH89792-2 MH89792-3 MT8941 MT8979 MT9042 MT9079
Text: MH89792 E1 Transceiver Preliminary Information Features ISSUE 3 April 1995 Ordering Information • Complete primary rate 2048kb/s CEPT line driver and receiver MH89792-1 MH89792-2 MH89792-3 • Onboard pulse transformers for transmit and receive • Meets latest ETSI requirements ETSI ETS 300
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Original
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PDF
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MH89792
2048kb/s
MH89792-1
MH89792-2
MH89792-3
330mm
MH89792
square root extractor
RXB 24
MH89792-1
MH89792-2
MH89792-3
MT8941
MT8979
MT9042
MT9079
|
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square root extractor
Abstract: 6 pin pulse transformer MH89793 120R MT9042 MT9079 PCM30 E1 frame square root extractor application
Text: MH89793 E1 Transceiver with Selectable Impedance Preliminary Information Features ISSUE 1 April 1995 Ordering Information • Complete primary rate 2048kb/s CEPT line driver and receiver MH89793 28 Pin DIL Package Surface Mount Option is available by adding
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Original
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PDF
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MH89793
2048kb/s
MH89793
MT9079
square root extractor
6 pin pulse transformer
120R
MT9042
PCM30
E1 frame
square root extractor application
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Untitled
Abstract: No abstract text available
Text: DS1249W 3.3V 2048kb Nonvolatile SRAM www.maxim-ic.com FEATURES § § § § § § § § PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation
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Original
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PDF
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DS1249W
2048kb
100ns
32-pin
100pF
150ns
DS1249W
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Untitled
Abstract: No abstract text available
Text: IßTEXAR X R -T 6 166 Codirectional Digital Data Processor FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The XR-T6166 is a digital CM O S circuit which performs the interface function betweeh a 64kbit/s data stream and a 2048kbit/s PCM timeslot data channel. When
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OCR Scan
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PDF
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XR-T6166
64kbit/s
2048kbit/s
XR-T6164,
XR-T6166
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Untitled
Abstract: No abstract text available
Text: MH89792 MITEL E1 Line Interface Unit LIU Preliminary Information Features • ISSUE 4 Complete prim ary rate 2048kbit/s E1 line driver and receiver with clock recovery MH89792-1 MH89792-2 Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transm it and
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OCR Scan
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PDF
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MH89792
2048kbit/s
MH89792-1
MH89792-2
MT8979,
MT9079
490mm2
MH89792
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Untitled
Abstract: No abstract text available
Text: J T E X A R XR-T6165 Codirectional Digital Data Processor PIN ASSIGNMENT GENERAL DESCRIPTION The XR-T6165 is a digital CMOS circuit which performs the interface function between a 64Kbit/s data stream and a 2048Kbit/s PCM timeslot data channel. When used in
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OCR Scan
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PDF
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XR-T6165
XR-T6165
64Kbit/s
2048Kbit/s
XR-T6164,
64Kbit/s
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clock alarm circuit diagram
Abstract: No abstract text available
Text: 22* E X 4 R XR-T6166 Codirectional Digital Data Processor FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The XR-T6166 is a digital CMOS circuit which performs the interface function between a 64Kbit/s data stream and a 2048Kbit/s PCM timeslot data channel. When used in
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OCR Scan
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PDF
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XR-T6166
64Kbit/s
2048Kbit/s
XR-T6164,
clock alarm circuit diagram
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Untitled
Abstract: No abstract text available
Text: EX4R XR-T6165 Codirectional Digital Data Processor PIN ASSIGNMENT GENERAL DESCRIPTION The XR-T6165 is a digital CMOS circuit which performs the interface function between a 64Kbit/s data stream and a 2048Kbit/s PCM timeslot data channel. When used in conjunction with the XR-T6164, the XR-T6165 conforms
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OCR Scan
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PDF
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XR-T6165
64Kbit/s
2048Kbit/s
XR-T6164,
XR-T6165
|
Untitled
Abstract: No abstract text available
Text: E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features ISSUE 2 • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery • Meets ETSI requirements [ETSI ETS 300 011, NET 5] • Built-in selectable term ination impedance
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OCR Scan
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PDF
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2/75a)
MT8979,
MT9079
MH89793
2048kbit/s
b24T370
MH89793
bS4T37Q
0012QÃ
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Untitled
Abstract: No abstract text available
Text: XR-T6166 Codirectional Digital Data Processor FUNCTIONAL BLOCK DIAGRAM G EN ERA L DESCRIPTION The XR-T6166 is a digital CM OS circuit which performs the interface function between a 64Kbit/s data stream and a 2048Kbit/s PCM tim eslot data channel. When used in
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OCR Scan
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PDF
|
XR-T6166
XR-T6166
64Kbit/s
2048Kbit/s
XR-T6164,
64Kbit/s
|
square root extractor
Abstract: No abstract text available
Text: @M|TEL MH89792 E1 Transceiver Preliminary Information O rdering Inform ation • Com plete prim ary rate 2048kb/s CEPT line driver and receiver • O nboard pulse transform ers fo r transm it and receive • Meets latest ETSI requirem ents ETSI ETS 300 011 (NET 5
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OCR Scan
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PDF
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2048kb/s
MH89792-1
MH89792-2
MH89792-3
MH89792
MH89792
MT9042
0G115SÔ
MHB9792
square root extractor
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