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    Text: SN74LVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE S C A S 2 8 4 -JANUARY 1 9 9 3 -R E V IS E D MARCH 1994 D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C


    OCR Scan     		SN74LVC10 SCAS284-JANUARY 1993-REVISED SN74LVC10 -100mA 010044M PDF