74HC109
Philips Semiconductors
Dual J invertedK flip-flop with set and reset positive-edge trigger
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74HC109
Philips Semiconductors
positive-edge trigger
Original
PDF
74HC109D
Philips Semiconductors
Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger
Original
PDF
74HC109D
Unknown
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
Historical
PDF
74HC109D,652
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax : 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT109-1 (SO16); Container: Bulk Pack, CECC
Original
PDF
74HC109D,653
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax : 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT109-1 (SO16); Container: Reel Pack, SMD, 13", CECC
Original
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74HC109D/AUJ
Philips Semiconductors
Logic - Flip Flops, Integrated Circuits (ICs), IC FLIP FLOP DUAL J-K 16SOIC
Original
PDF
74HC109DB
Philips Semiconductors
Dual J inverted(K) flip-flop with set and reset, positive-edge trigger
Original
PDF
74HC109DB
Unknown
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
Historical
PDF
74HC109DB,112
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax : 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT338-1 (SSOP16); Container: Tube
Original
PDF
74HC109DB,118
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax : 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13"
Original
PDF
74HC109DB-T
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax : 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V
Original
PDF
74HC109DB-T
Unknown
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
Historical
PDF
74HC109D-Q100J
Nexperia USA
Uncategorized - Miscellaneous - 74HC109D-Q100/SOT109/SO16
Original
PDF
74HC109D-T
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax : 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V
Original
PDF
74HC109D-T
Unknown
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
Historical
PDF
74HC109DW
Philips Semiconductors
Dual J inverted(K) flip-flop with set and reset, positive-edge trigger
Original
PDF
74HC109N
Philips Semiconductors
Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger
Original
PDF
74HC109N
Unknown
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
Historical
PDF
74HC109N,652
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax : 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT38-4 (DIP16); Container: Bulk Pack, CECC
Original
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